The present invention relates to an amplification-type solid-state image pickup device, and more specifically relates to an amplification-type solid-state image pickup device incorporating a plurality of arrayed pixels with an amplification function.
There has been proposed an amplification-type solid-state image pickup device having a pixel portion in which each pixel has an amplification function and a scanning circuit disposed around the pixel portion, the pixel portion being scanned by the scanning circuit so that each pixel data is read out. Particularly, there is known an APS (Active Pixel Sensor)-type image sensor having a pixel constitution composed of a CMOS that offers advantage in integrating the pixel constitution with peripheral driver circuit and signal processing circuit.
Generally, the APS-type image sensor is constituted such that a photon-electron conversion portion, an amplification portion, a pixel selection portion and a reset portion are provided in one pixel. The photon-electron conversion portion is typically formed from a photo diode (PD), while the amplification portion, the pixel selection portion and the reset portion are formed from three to four MOS-type transistors (Tr).
In FIG. 14, there is shown a constitution of an APS-type image sensor of a (PD+3Tr) type composed of one photodiode (PD) and three MOS transistors (Tr) (to simplify the drawing, the pixel portion shown therein is composed of only 2 rows and 2 columns (4 pixels)). In FIG. 14, there are shown an amplification MOS transistor 201, a reset MOS transistor 202, a pixel selection MOS transistor 203, a photon-electron conversion photodiode 204, a signal line 205, a power line 206, a pixel selection line 207 and a reset gate line 280. The MOS transistors 203 and 202 are respectively driven by a vertical scanning circuit (I) 221 and a vertical scanning circuit (IIo) 222 through the pixel selection line 207 and the reset gate line 280. The signal line 205 is connected to the MOS transistor 230 that supplies a constant-current load (a voltage of VL1 is applied as a gate bias voltage), and the output voltage is sent to a horizontal signal line 236 through an amplifier (amplification-type MOS transistor) 231 and a MOS transistor 232. The MOS transistor 232 is driven by a horizontal scanning circuit 234 through a horizontal clock line 235. The horizontal signal line 236 is connected to a MOS transistor 233 that supplies a constant-current load (a voltage of VL2 is applied as a gate bias voltage), and the output voltage is lead to an output OS through an amplifier 237.
As shown in FIG. 15 with the above-described pixel constitution, if VDD<φRH where a channel potential below the reset gate is set to φRH and a reset drain voltage is set to VDD when a gate (reset gate) of the reset transistor 202 is in ON state, then a voltage of the photodiode 204 is reset to VDD when the reset gate is in ON state. However, after the reset gate is turned off, the photodiode suffers from noise ΔNrn expressed in electron number as shown in the following equation (1).ΔNrn=(kTCp)1/2/q  (1)wherein k represents a Boltzman's constant, T represents an absolute temperature, Cp represents the capacity of the photodiode and a region connected thereto, and q represents an elementary charge. As is clear from the equation (1), the reset noise is dependent on the capacity Cp and rises as Cp increases.
As is clear from FIG. 14, Cp includes not only the capacity of the photodiode itself but also the gate capacity of the amplification MOS transistor 201 and their reciprocal connection capacity. Because of this, the above-constituted pixel requires reduction in the reset noise ΔNrn.
In order to reduce the reset noise, a soft reset operation as described below has been proposed (see, e.g., “Analysis and enhancement of low-light level performance of photodiode-type CMOS active pixel imagers operated with sub-threshold reset” by Bedabrata Pain et al. in IEEE Workshop on Charge-Coupled Devices and Advanced Image Sensors, June 1999, p140–143). More specifically, as shown in FIG. 16, if VDD>φRH when the gate (reset gate) of the reset transistor 202 is in ON state, then the potential of the photodiode 204 is reset to a sub-threshold region in the vicinity of φRH. In this case, after the reset gate is turned off, the photodiode suffers from noise ΔNrn expressed in electron number as shown in the following equation (2).ΔNrn=(kTCp/2)1/2/q  (2)
In this case, the noise expressed in electron number is reduced to (½)1/2=0.71 of the noise in the equation (1).
However, if the potential of the reset drain 206 is fixed to VDD by the soft reset operation, leakage in the reset gate due to sub-threshold current disables the potential of the photodiode from being fixed, substantially causing image retention for as a very long period of time as not less than 10 frames.
In order to avoid the phenomenon of image retention, a method of performing a hard reset operation before the soft reset operation has been proposed. FIG. 17 shows its circuit constitution, and FIG. 18 shows its operation timing. In this method, before the soft reset operation, the reset drain potential is once set to a potential (VDD−Δφm) lower than φRH. This fixes the potential of the photodiode to (VDD−Δφm) so that the potential of the photodiode displaced by the leakage due to the sub-threshold current is fixed with respect to each storage period, thereby preventing the image retention from occurring.
As shown in FIG. 17, the circuit constitution in this case is different from the circuit constitution shown in FIG. 14 in the point that not a DC (Direct Current) but a pulsed potential VP(i) is applied to a power line 310. More specifically, the potential VP(i) is changed between two values by transistors 311, 312 and the pulse VPo(i). That is, when VPo(i) is in low level, the transistor 311 is turned on to make VP(i)=VDD. When VPo(i) is in high level, the transistor 311 is turned off, and applied to the power line 310 is a voltage decreased from VDD by a potential drop portion Δφm of the transistor 312 as shown below.VP(i)=VDD−Δφm
As shown in FIG. 18, a reset period (T11+T12) is set when RS(i) becomes high level. In the former half period T11, VP(i)=VDD−Δφm, so that setting VDD−Δφm<φRH fixes the potential of the photodiode to (VDD−Δφm). This means that the hard reset operation is performed. Next, in the latter half period T12, VP(i)=VDD, so that setting VDD>φRH allows the soft reset operation of the photodiode. Herein, signal level read is executed before the reset period (T11+T12), while reset level read is executed after the reset period (T11+T12).
However, although in the method of executing the hard reset operation before the soft reset operation described with reference to FIGS. 17 and 18, image retention can be avoided, the reset noise is, as shown in the equation (2), at best reduced to 0.71 times the level of the noise in electron number generated in the typical reset operation, which is the noise level insufficient for high-resolution image sensors.